OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] - Rev 207

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
207 Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin) olivier.girard 3152d 11h /
206 Update ChangeLog olivier.girard 3249d 11h /
205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3249d 11h /
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3256d 11h /
203 Update ChangeLog olivier.girard 3263d 10h /
202 Add DMA interface support + LINT cleanup olivier.girard 3263d 11h /
201 Update ChangeLog olivier.girard 3424d 10h /
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3424d 10h /
199 Update ChangeLog olivier.girard 3530d 12h /
198 Update GDB-Proxy to support new GCC/GDB compiler version from RedHat/TI olivier.girard 3530d 12h /
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3781d 11h /
196 Update ChangeLog olivier.girard 3824d 10h /
195 Update HTML documentation with configurable number of IRQ option. olivier.girard 3824d 10h /
194 Update PDF and ODT documentation. olivier.girard 3824d 11h /
193 Update FPGA projects with latest core RTL changes. olivier.girard 3824d 11h /
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3824d 12h /
191 Update ChangeLog olivier.girard 3964d 11h /
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3964d 11h /
189 Update ChangeLog olivier.girard 3976d 11h /
188 Add missing include commands for the define and undefine files in the wakeup_cell and in dbg_i2c. olivier.girard 3976d 11h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.