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Rev Log message Author Age Path
209 Update ChangeLogs olivier.girard 3149d 23h /
208 Update tools to run with latest CPU core version. olivier.girard 3149d 23h /
207 Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin) olivier.girard 3149d 23h /
206 Update ChangeLog olivier.girard 3246d 23h /
205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3246d 23h /
204 Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that). olivier.girard 3253d 23h /
203 Update ChangeLog olivier.girard 3260d 22h /
202 Add DMA interface support + LINT cleanup olivier.girard 3260d 22h /
201 Update ChangeLog olivier.girard 3421d 22h /
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3421d 22h /
199 Update ChangeLog olivier.girard 3528d 00h /
198 Update GDB-Proxy to support new GCC/GDB compiler version from RedHat/TI olivier.girard 3528d 00h /
197 Fixed bug on the write strobe of the baudrate hi configuration register. olivier.girard 3778d 23h /
196 Update ChangeLog olivier.girard 3821d 22h /
195 Update HTML documentation with configurable number of IRQ option. olivier.girard 3821d 22h /
194 Update PDF and ODT documentation. olivier.girard 3821d 23h /
193 Update FPGA projects with latest core RTL changes. olivier.girard 3821d 23h /
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3821d 23h /
191 Update ChangeLog olivier.girard 3961d 23h /
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3961d 23h /

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