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Rev Log message Author Age Path
27 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5313d 14h /
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.
olivier.girard 5313d 14h /
25 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5403d 12h /
24 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5403d 12h /
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).
olivier.girard 5424d 10h /
22 Updated some links in the HTML documentation. olivier.girard 5437d 07h /
21 added discussion group info olivier.girard 5449d 08h /
20 added some SVN ignore patterns.
small update to html documentation
olivier.girard 5450d 04h /
19 added SVN property for keywords olivier.girard 5450d 05h /
18 Updated headers with SVN info olivier.girard 5450d 05h /
17 Updated header with SVN info olivier.girard 5450d 05h /
16 Updated header with SVN info olivier.girard 5450d 05h /
15 Updated headers with SVN info olivier.girard 5450d 06h /
14 Updated headers with SVN info olivier.girard 5450d 06h /
13 Completed PDF documentation olivier.girard 5450d 06h /
12 some more typo fixes... olivier.girard 5452d 06h /
11 aesthetic changes olivier.girard 5456d 06h /
10 Update software development tools documentation olivier.girard 5456d 06h /
9 Added pictures for the software development tools documentation olivier.girard 5456d 06h /
8 Created ODT document olivier.girard 5461d 06h /

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