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Rev Log message Author Age Path
31 Update documentation (new Altera FPGA project + diverse minor updates) olivier.girard 5321d 19h /
30 Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution). olivier.girard 5321d 19h /
29 Add Altera Cyclone II FPGA project example. olivier.girard 5321d 20h /
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5330d 03h /
27 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5330d 03h /
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5330d 04h /
25 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5420d 01h /
24 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5420d 01h /
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5440d 23h /
22 Updated some links in the HTML documentation. olivier.girard 5453d 21h /
21 added discussion group info olivier.girard 5465d 22h /
20 added some SVN ignore patterns.
small update to html documentation		 olivier.girard 5466d 18h /
19 added SVN property for keywords olivier.girard 5466d 18h /
18 Updated headers with SVN info olivier.girard 5466d 18h /
17 Updated header with SVN info olivier.girard 5466d 19h /
16 Updated header with SVN info olivier.girard 5466d 19h /
15 Updated headers with SVN info olivier.girard 5466d 19h /
14 Updated headers with SVN info olivier.girard 5466d 20h /
13 Completed PDF documentation olivier.girard 5466d 20h /
12 some more typo fixes... olivier.girard 5468d 19h /

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