Rev |
Log message |
Author |
Age |
Path |
493 |
ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. |
julius |
4867d 14h |
/ |
492 |
ORPSoC VPI interface for modelsim and documentation update |
julius |
4868d 12h |
/ |
491 |
ORPSoC or1200_monitor update. |
julius |
4868d 23h |
/ |
490 |
Updates to fix spurious test failures and register scheduling. |
jeremybennett |
4873d 04h |
/ |
489 |
ORPSoC sw cleanup. Remove warnings. |
julius |
4878d 11h |
/ |
488 |
ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. |
julius |
4878d 12h |
/ |
487 |
ORPSoC main software makefile update |
julius |
4881d 09h |
/ |
486 |
ORPSoC updates, mainly software, i2c driver |
julius |
4881d 10h |
/ |
485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4885d 14h |
/ |
484 |
Changes to make r12 call-saved and to bring wchar tests in line. |
jeremybennett |
4886d 12h |
/ |
483 |
Updated with new opcodes to generate random numbers and to identify us as Or1ksim. |
jeremybennett |
4888d 14h |
/ |
482 |
Don't hardcode tool versions in help text |
olof |
4890d 02h |
/ |
481 |
OR1200 Update. RTL and spec. |
julius |
4901d 21h |
/ |
480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
4902d 18h |
/ |
479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4903d 18h |
/ |
478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4905d 10h |
/ |
477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4905d 18h |
/ |
476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4906d 11h |
/ |
475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4906d 14h |
/ |
474 |
uC/OS-II port linker flags updated. |
julius |
4906d 19h |
/ |