URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 80

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
80	Add missing configuration files to SVN.	jeremybennett	5250d 16h	/
79	Fixed retry loop in or_debug_proxy, hopefully more stable when physically resetting the board	julius	5262d 17h	/
78	Fixed typo in Silos workaround script	rherveille	5263d 12h	/
77	Added support for Silvaco's Silos simulator Added workaround for Silos's exit code behaviour	rherveille	5263d 13h	/
76	Added: +libext+.v Added: +incdir+.	rherveille	5264d 12h	/
75	Fixed toolchain script's cygwin ncurses check	julius	5269d 15h	/
74	Toolchain script fix for ncurses header checking	julius	5287d 17h	/
73	toolchain script error fix	julius	5287d 18h	/
72	Toolchain install script: or1ksim location changed, few tweaks	julius	5290d 15h	/
71	ORPSoC board builds, adding readmes	julius	5306d 22h	/
70	ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\!	julius	5311d 03h	/
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5311d 04h	/
68	Fixed up a couple of Makefile things in ORPSoCv2	julius	5313d 19h	/
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5313d 22h	/
66	Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software.	julius	5333d 20h	/
65	ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix	julius	5338d 02h	/
64	Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile.	julius	5340d 21h	/
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5350d 18h	/
62	This material is part of the separate website downloads directory.	jeremybennett	5361d 22h	/
61	The build directory should not be part of the SVN configuration.	jeremybennett	5361d 22h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories openrisc

[/] - Rev 80

Filtering Options