OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] - Rev 344

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
344 Directory for tagging newlib 1.18.0 jeremybennett 5187d 22h /
343 Build C++ and its libraries. jeremybennett 5188d 00h /
342 Various files regenerated as part of RC1 creation. jeremybennett 5188d 00h /
341 Tagging the 1.0rc1 candidate release of GDB 7.2 jeremybennett 5188d 02h /
340 Tag directory for GDB 7.2. jeremybennett 5188d 02h /
339 Updates for GDB 7.2 for OpenRISC version 1.0 release candidate 1. OpenRISC
documentation subsumes the old separate OpenRISC document.
jeremybennett 5188d 05h /
338 Tagging the 1.0rc1 candidate release of GCC 4.5.1 jeremybennett 5188d 21h /
337 Directory for GCC 4.5.1 tags jeremybennett 5188d 21h /
336 Corrected for 4.5.1-or32-1.0rc1 jeremybennett 5188d 22h /
335 Updated version number to 4.5.1-or32-1.0. jeremybennett 5188d 22h /
334 Record changes to the documentation and option handling. jeremybennett 5188d 22h /
333 Fix the default option (to use -mhard-mul). Update the documentation for
OpenRISC.
jeremybennett 5188d 22h /
332 Provide support for nested functions. Tidy up board specification.

* config/or32/or32-protos.c <or32_trampoline_code_size>: Added.
* config/or32/or32.c <OR32_MOVHI, OR32_ORI, OR32_LWZ, OR32_JR>:
New macros added.
(or32_emit_mode, or32_emit_binary, or32_force_binary)
(or32_trampoline_code_size, or32_trampoline_init): Created.
(or32_output_bf): Tabbing fixed.
<TARGET_TRAMPOLINE_INIT>: Definition added.
* config/or32/or32.h <STATIC_CHAIN_REGNUM>: Uses R11.
<TRAMPOLINE_SIZE>: redefined.
<TRAMPOLINE_ENVIRONMENT>: Added definition.
jeremybennett 5189d 22h /
331 Updated for GDB 7.2 and GCC 4.5.1 (which needs target-libgcc). jeremybennett 5190d 06h /
330 Baseline port of GDB 7.2 for OpenRISC 1000 jeremybennett 5190d 17h /
329 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5190d 17h /
328 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5190d 17h /
327 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5190d 17h /
326 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5190d 17h /
325 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5190d 17h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.