URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 1096

Rev	Log message	Author	Age	Path
1096	An example of SW and RTL regression log because many people asked for.	lampret	7897d 07h	/
1095	eval_reg replaced with the new evalsim_reg32	lampret	7898d 03h	/
1094	sys/time.h might not be available for or1k target	lampret	7898d 05h	/
1093	New UART rx/tx fiel settings (due to or1ksim upgrade)	lampret	7898d 05h	/
1092	Changed from or32-rtems toolchain to or32-uclinux.	lampret	7898d 05h	/
1091	Added mmu test.	lampret	7898d 05h	/
1090	Removed ic_invalidate	lampret	7898d 05h	/
1089	Added dhrystone 2.1 benchmark	lampret	7898d 05h	/
1088	Changed from or32-rtems toolchain to or32-uclinux.	lampret	7898d 05h	/
1087	Changed or32-rtems to or32-uclinux.	lampret	7898d 05h	/
1086	STACK_ARGS is getting obsolete and is only needed by simprintf, which needs it to be 0.	lampret	7898d 05h	/
1085	Bug fixed.	simons	7903d 09h	/
1084	This commit was manufactured by cvs2svn to create tag 'rel_8'.		7917d 17h	/
1083	SB mem width fixed.	simons	7917d 17h	/
1082	channels integration	rprescott	7918d 05h	/
1081	or32-uclinux tool chain have to be used to build the testbench.	simons	7925d 21h	/
1080	This commit was manufactured by cvs2svn to create tag 'rel_7'.		7926d 14h	/
1079	RAMs wrong connected to the BIST scan chain.	mohor	7926d 14h	/
1078	Previous check-in was done by mistake.	mohor	7926d 15h	/
1077	Signal scanb_sen renamed to scanb_en.	mohor	7926d 16h	/