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Rev Log message Author Age Path
1191 disabled 'bench_defines.v' during synthesis +
added define to specify usage of flash instruction address
dries 7574d 10h /
1190 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7590d 09h /
1189 This commit was manufactured by cvs2svn to create tag 'rel_13'. 7590d 09h /
1188 Added support for rams with byte write access. simons 7590d 09h /
1187 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7591d 08h /
1186 Added support for rams with byte write access. simons 7591d 08h /
1185 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7598d 01h /
1184 Scan signals mess fixed. simons 7598d 01h /
1183 OpenRISC port of gdb-5.3 straightforwardly derived from gdb-5.0 sfurman 7602d 16h /
1182 This commit was manufactured by cvs2svn to create tag 'VER_5_3'. 7602d 19h /
1181 Initial import of unmodified gdb-5.3 source on vendor branch sfurman 7602d 19h /
1180 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7606d 04h /
1179 BIST interface added for Artisan memory instances. simons 7606d 04h /
1178 avoid another immu exception that should not happen phoenix 7635d 16h /
1177 more informative output phoenix 7636d 22h /
1176 Added comments. damonb 7637d 13h /
1175 Added three missing wire declarations. No functional changes. lampret 7637d 16h /
1174 fix for immu exceptions that never should have happened phoenix 7638d 17h /
1173 Added QMEM. lampret 7640d 01h /
1172 Added embedded memory QMEM. lampret 7640d 02h /

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