OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 1604

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
1604 Fix dumphex/dumpverilog to not do unaligned memory access nogj 6773d 04h /
1603 Accept EM_OPENRISC as a valid machine nogj 6774d 08h /
1602 Corrected description of l.sfXXui (arch manual had a wrong description compared to behavior implemented in or1ksim/gcc/or1200). Removed Atomicity chapter. lampret 6775d 06h /
1601 fixed description of l.sfXXXi lampret 6775d 06h /
1600 Corrected mistake in pin assignation due to typo error in RC203 manual jcastillo 6783d 07h /
1599 Corrected Syn Script to add MMU memories jcastillo 6783d 14h /
1598 Handle ethernet addresses as an address and not as an int nogj 6785d 05h /
1597 Fix parsing the destination register nogj 6785d 05h /
1596 Fix handling of eof in the sim cli nogj 6785d 05h /
1595 Add default immu/dmmu page size nogj 6785d 06h /
1594 Fix the case of is_power2(0) nogj 6785d 06h /
1593 Don't kill sim on second ctrl+c if the cli prompt has already been shown nogj 6785d 06h /
1592 Added additional desc of tick timer, added l.fl1, corrected desc of l.ff1 and corrected encoding of l.maci lampret 6787d 08h /
1591 Added l.fl1, fixed desc of l.ff1 lampret 6788d 03h /
1590 Added l.fl1 lampret 6788d 03h /
1589 Make -d channel be equivalent to -d +channel nogj 6791d 14h /
1588 Correct INT_MAX->INT32_MAX nogj 6791d 15h /
1587 Supports two RAM banks by Jacob Bower jcastillo 6795d 04h /
1586 Charles Qi
Fix memory handling on big endian machines
nogj 6796d 07h /
1585 added missing exception, fixes segfault with trap exception phoenix 6802d 00h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.