URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 1623

Rev	Log message	Author	Age	Path
1623	First Import of uClinux for RC20x board	jcastillo	6744d 10h	/
1622	First Import of uClinux for RC20x board	jcastillo	6744d 10h	/
1621	First Impot	jcastillo	6744d 11h	/
1620	Added SMC91C111 LAN Chip Interruption to work with uClinux	jcastillo	6749d 07h	/
1619	Fixed types in function declaration	jcastillo	6749d 12h	/
1618	Import of or32 sepcific part of binutils port updated by Balint and Nog	phoenix	6749d 19h	/
1617	* empty log message *	phoenix	6749d 19h	/
1616	Import of or32 sepcific part of binutils port updated by Balint and Nog	phoenix	6749d 19h	/
1615	* empty log message *	phoenix	6749d 19h	/
1614	CI should not be set in dMMU translation tables or one gets different behaviour with dMMU on or off in case data cache is enabled. care should be taken for addresses higher than 0x7fff_ffff where the situation is just reversed. (since or1200 does not cache upper half of address space if there is no dMMU)	phoenix	6759d 20h	/
1613	change default	phoenix	6765d 05h	/
1612	major optimizations for or32 target	phoenix	6765d 05h	/
1611	This commit was manufactured by cvs2svn to create tag 'stable_0_2_0_rc2'.		6768d 07h	/
1610	Update ChangeLog	nogj	6768d 07h	/
1609	0.2.0-rc2 release	nogj	6768d 07h	/
1608	Avoid scheduleing too many jobs, potentially underflowing the scheduler stack	nogj	6769d 01h	/
1607	Don't drop cycles from the scheduler	nogj	6769d 01h	/
1606	fix uninitialized reads	phoenix	6769d 06h	/
1605	Execute l.ff1 instruction	nogj	6776d 02h	/
1604	Fix dumphex/dumpverilog to not do unaligned memory access	nogj	6776d 02h	/