URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 1632

Rev	Log message	Author	Age	Path
1632	First Import of RC20x uClinux	jcastillo	6741d 18h	/
1631	First Import	jcastillo	6741d 18h	/
1630	* empty log message *	jcastillo	6741d 18h	/
1629	First Import of uClinux for RC20x board	jcastillo	6741d 18h	/
1628	First Import of uClinux for RC20x board	jcastillo	6741d 19h	/
1627	First Import of RC20x uClinux	jcastillo	6741d 19h	/
1626	First Import of uClinux for RC20x board	jcastillo	6741d 19h	/
1625	First Import of uClinux for RC20x board	jcastillo	6741d 19h	/
1624	First Import of uClinux for RC20x board	jcastillo	6741d 19h	/
1623	First Import of uClinux for RC20x board	jcastillo	6741d 19h	/
1622	First Import of uClinux for RC20x board	jcastillo	6741d 20h	/
1621	First Impot	jcastillo	6741d 21h	/
1620	Added SMC91C111 LAN Chip Interruption to work with uClinux	jcastillo	6746d 16h	/
1619	Fixed types in function declaration	jcastillo	6746d 21h	/
1618	Import of or32 sepcific part of binutils port updated by Balint and Nog	phoenix	6747d 04h	/
1617	* empty log message *	phoenix	6747d 04h	/
1616	Import of or32 sepcific part of binutils port updated by Balint and Nog	phoenix	6747d 04h	/
1615	* empty log message *	phoenix	6747d 04h	/
1614	CI should not be set in dMMU translation tables or one gets different behaviour with dMMU on or off in case data cache is enabled. care should be taken for addresses higher than 0x7fff_ffff where the situation is just reversed. (since or1200 does not cache upper half of address space if there is no dMMU)	phoenix	6757d 05h	/
1613	change default	phoenix	6762d 14h	/