OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 24

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
24 Static branch prediction added. lampret 8808d 15h /
23 Common OR1K backend for OR32 and OR16. lampret 8808d 15h /
22 More modifications related to or16. lampret 8810d 21h /
21 More modifications related to or16. cmchen 8810d 21h /
20 or1k renamed to or32. lampret 8811d 10h /
19 Added or16, or1k renamed to or32. lampret 8811d 10h /
18 or16 added, or1k renamed to or32. lampret 8811d 11h /
17 Re-generated. jrydberg 8834d 07h /
16 Add support for systems without readline. To use GNU readline library,
use the `--enable-readline' option to the configure script.
jrydberg 8834d 07h /
15 Initial revision. jrydberg 8870d 21h /
14 First import. lampret 8871d 00h /
13 Rebuild of the generated files. jrydberg 8872d 03h /
12 Added information to the section about how to configure and compile
the package.
jrydberg 8872d 03h /
11 Rebuild from configure.in. jrydberg 8872d 03h /
10 Support for both architectures. Specify architecture with the
--target option.
jrydberg 8872d 03h /
9 Added support for OpenRISC 100 and DLX. jrydberg 8872d 03h /
8 Initial revision. jrydberg 8872d 03h /
7 Major update of the enviorment. Now uses autoconf and automake. The
simulator uses readline aswell to get input from the user. A number of
new files added, some modified. The libc directory is now called support.
jrydberg 8872d 03h /
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8872d 21h /
5 Data and instruction cache simulation added. lampret 8872d 21h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.