OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 265

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
265 Modified virtual silicon instantiations. lampret 8256d 19h /
264 updated cpu config section; added sim config section markom 8256d 23h /
263 configure for cpu; modified command line options markom 8257d 00h /
262 small bug in build_automata fixed; configure for memory markom 8257d 01h /
261 modified memory accesses; added cfg script; added pic test basic entry of vga; some extensions to mc markom 8257d 03h /
260 Replaced some 8-bit memory access with 32-bit erez 8258d 17h /
259 Removed tick/Makefile, which is generated anyway erez 8258d 20h /
258 Added Ethernet test; renamed dma to dmatest; commented out missing pic.c erez 8258d 20h /
257 Added initial Ethernet simulation (only TX as yet) erez 8258d 20h /
256 fixed masked_increase() in dma.c erez 8258d 20h /
255 mtspr() now correctly sets value to register erez 8258d 23h /
254 Made error report more verbose erez 8258d 23h /
253 Made macros slightly more robust erez 8259d 00h /
252 Fixed typo erez 8259d 00h /
251 "Granularity" bugfix erez 8259d 00h /
250 This commit was manufactured by cvs2svn to create tag 'or1ksim-ss-20000302'. 8261d 09h /
249 This commit was manufactured by cvs2svn to create tag 'or1k-1_0'. 8261d 09h /
248 First import. cvs 8261d 09h /
247 Major update of the enviorment. Now uses autoconf and automake. The
simulator uses readline aswell to get input from the user. A number of
new files added, some modified. The libc directory is now called support.
jrydberg 8261d 09h /
246 This commit was manufactured by cvs2svn to create branch 'oc'. 8261d 09h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.