OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 350

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
350 For GDB changed single stepping and disabled trap exception. lampret 8265d 02h /
349 Some bugs regarding cache simulation fixed. simons 8266d 15h /
348 Added instructions on how to build configure. ivang 8267d 22h /
347 Added CRC32 calculation to Ethernet erez 8268d 20h /
346 Improved Ethernet simulation erez 8268d 21h /
345 Added check for net/ethernet.h (needed by ethernet simulator) erez 8268d 21h /
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8268d 23h /
343 Small touches to test programs erez 8269d 01h /
342 added exception vectors to support and modified section names markom 8269d 22h /
341 added VAPI for uart; uart 16550 support, some bugs fixed markom 8270d 00h /
340 Added hpint vector lampret 8270d 01h /
339 Added setpc test lampret 8270d 01h /
338 Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) lampret 8270d 01h /
337 Fixed tick timer interrupt reporting by using TTCR[IP] bit. lampret 8270d 01h /
336 VAPI works markom 8270d 20h /
335 some small bugs fixed markom 8270d 21h /
334 removed vapi client file markom 8271d 00h /
333 small bug fixed markom 8271d 03h /
332 removed fixed irq numbering from pic.h; tick timer section added markom 8271d 03h /
331 dependecy is required by history analisis markom 8271d 04h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.