URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 792

Rev	Log message	Author	Age	Path
792	Fixed port names that changed.	lampret	8132d 12h	/
791	Fixed some ports in instnatiations that were removed from the modules	lampret	8132d 12h	/
790	Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives	lampret	8132d 12h	/
789	Added response from memory controller (addr 0x60000000)	lampret	8132d 13h	/
788	Some of the warnings fixed.	lampret	8132d 14h	/
787	Added romfs.tgz	lampret	8133d 08h	/
786	Moved UCF constraint file to the backend directory.	lampret	8133d 08h	/
785	Added XSV specific documentation.	lampret	8133d 08h	/
784	Added soem missing files.	lampret	8133d 08h	/
783	Added sim directory and sub files/dirs.	lampret	8133d 08h	/
782	Added the old SW directory. It needs to be updated for the new ORP environment and test cases moved to sw directory.	lampret	8133d 08h	/
781	Added design compiler scripts. However these are not ready for use yet .... They need to be updated for the ORP sources and ORP sources need to be updated as well.	lampret	8133d 09h	/
780	Added libraries.	lampret	8133d 09h	/
779	Added bench directory	lampret	8133d 09h	/
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8133d 09h	/
777	Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2	lampret	8133d 10h	/
776	Updated defines.	lampret	8133d 10h	/
775	Optimized cache controller FSM.	lampret	8133d 10h	/
774	Removed old files.	lampret	8133d 10h	/
773	Changing directory structure ...	lampret	8133d 11h	/