URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 806

Rev	Log message	Author	Age	Path
806	uart now partially uses scheduler	markom	8088d 19h	/
805	kbd, fb, vga devices now uses scheduler	markom	8088d 20h	/
804	memory regions can now overlap with MC -- not according to MC spec	markom	8089d 14h	/
803	Free irq handler fixed.	simons	8092d 07h	/
802	Cache and tick timer tests fixed.	simons	8093d 18h	/
801	l.muli instruction added	markom	8095d 14h	/
800	Bug fixed.	simons	8096d 12h	/
799	Wrapping around 512k boundary to simulate real hw.	simons	8100d 05h	/
798	Hardware scroll added. This possible due to the fact that crt is wrapping around 512k boundary.	simons	8100d 05h	/
797	Changed hardcoded address for fake MC to use a define.	lampret	8100d 06h	/
796	Removed unused ports wb_clki and wb_rst_i	lampret	8100d 06h	/
795	Added a directive to ignore signed division variables that are only used in simulation.	lampret	8100d 10h	/
794	Added again just recently removed full_case directive	lampret	8100d 11h	/
793	Added synthesis off/on for timescale.v included file.	lampret	8100d 11h	/
792	Fixed port names that changed.	lampret	8100d 11h	/
791	Fixed some ports in instnatiations that were removed from the modules	lampret	8100d 11h	/
790	Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives	lampret	8100d 11h	/
789	Added response from memory controller (addr 0x60000000)	lampret	8100d 11h	/
788	Some of the warnings fixed.	lampret	8100d 12h	/
787	Added romfs.tgz	lampret	8101d 06h	/