URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 81

Rev	Log message	Author	Age	Path
81	This commit was manufactured by cvs2svn to create tag 'alpha'.		8491d 20h	/
80	First import.	lampret	8491d 20h	/
79	Data and instruction cache simulation added.	lampret	8493d 17h	/
78	(i/d)tlb_status	lampret	8617d 07h	/
77	Regular update.	lampret	8617d 07h	/
76	regular update	lampret	8617d 07h	/
75	simgetstr added. eval_mem32 replaced with evalsim_mem32.	lampret	8617d 07h	/
74	Same as DMMU.	lampret	8624d 06h	/
73	Fixed all bugs. Now more or less works. IMMU still has some problems (exception start).	lampret	8624d 06h	/
72	Added 'how to build GNU tools'	lampret	8629d 07h	/
71	Clean two typos.	lampret	8634d 09h	/
70	Basic setjmp/longjmp are ready.	lampret	8634d 09h	/
69	Sim debug.	lampret	8636d 06h	/
68	Added hook for l.sys 204. Changed SPR of flag (no more CCR)	lampret	8636d 07h	/
67	Added simulator "application load".	lampret	8636d 07h	/
66	Added another set of eval_ functions that should be used directly by simulator. evalsim_ and setsim_ don't go through MMU transaltion mechanism.	lampret	8636d 07h	/
65	Added DMMU stats.	lampret	8636d 07h	/
64	SPR bit definition moved to spr_defs.h.	lampret	8636d 07h	/
63	Fixed a bug in getsprbits/setsprbits functions (now mask can have arbitry alignment of bits).	lampret	8636d 07h	/
62	OR1K DMMU model.	lampret	8636d 07h	/