OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 811

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
811 This commit was manufactured by cvs2svn to create tag 'initial'. 8214d 06h /
810 This commit was generated by cvs2svn to compensate for changes in r809,
which included commits to RCS files with non-trunk default branches.
simons 8214d 06h /
809 ORP monitor simons 8214d 06h /
808 Elf support added. simons 8214d 07h /
807 sched files moved to support dir markom 8215d 09h /
806 uart now partially uses scheduler markom 8215d 09h /
805 kbd, fb, vga devices now uses scheduler markom 8215d 10h /
804 memory regions can now overlap with MC -- not according to MC spec markom 8216d 04h /
803 Free irq handler fixed. simons 8218d 21h /
802 Cache and tick timer tests fixed. simons 8220d 08h /
801 l.muli instruction added markom 8222d 04h /
800 Bug fixed. simons 8223d 02h /
799 Wrapping around 512k boundary to simulate real hw. simons 8226d 19h /
798 Hardware scroll added. This possible due to the fact that crt is wrapping around 512k boundary. simons 8226d 19h /
797 Changed hardcoded address for fake MC to use a define. lampret 8226d 20h /
796 Removed unused ports wb_clki and wb_rst_i lampret 8226d 20h /
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8227d 00h /
794 Added again just recently removed full_case directive lampret 8227d 01h /
793 Added synthesis off/on for timescale.v included file. lampret 8227d 01h /
792 Fixed port names that changed. lampret 8227d 01h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.