URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 994

Rev	Log message	Author	Age	Path
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	7955d 14h	/
993	Fixed IMMU bug.	lampret	7955d 14h	/
992	A bug when cache enabled and bus error comes fixed.	simons	7955d 23h	/
991	Different memory controller.	simons	7955d 23h	/
990	Test is now complete.	simons	7955d 23h	/
989	c++ is making problems so, for now, it is excluded.	simons	7957d 07h	/
988	ORP architecture supported.	simons	7957d 22h	/
987	ORP architecture supported.	simons	7958d 06h	/
986	outputs out of function are not registered anymore	markom	7958d 06h	/
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	7958d 18h	/
984	Disable SB until it is tested	lampret	7958d 18h	/
983	First checkin	lampret	7958d 20h	/
982	Moved to sim/bin	lampret	7958d 20h	/
981	First checkin.	lampret	7958d 20h	/
980	Removed sim.tcl that shouldn't be here.	lampret	7958d 20h	/
979	Removed old test case binaries.	lampret	7958d 20h	/
978	Added variable delay for SRAM.	lampret	7958d 20h	/
977	Added store buffer.	lampret	7958d 20h	/
976	Added store buffer	lampret	7958d 20h	/
975	First checkin	lampret	7958d 20h	/