OpenCores
URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] - Rev 975

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
975 First checkin lampret 7994d 03h /
974 Enabled what works on or1ksim and disabled other tests. lampret 7994d 05h /
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 7996d 09h /
972 Interrupt suorces fixed. simons 7996d 09h /
971 Now even keyboard test passes. simons 7996d 12h /
970 Testbench is now running on ORP architecture platform. simons 7997d 01h /
969 Checking in except directory. lampret 7997d 17h /
968 Checking in utils directory. lampret 7997d 17h /
967 Checking in mul directory. lampret 7997d 17h /
966 Checking in cbasic directory. lampret 7997d 17h /
965 Checking in basic directory. lampret 7997d 17h /
964 Checking in support directory. lampret 7997d 17h /
963 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7997d 17h /
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 7997d 17h /
961 uart16550 RTL files renamed/added/removed. lampret 7997d 17h /
960 Directory cleanup. lampret 7997d 17h /
959 Fixed size of generic flash/sram to exactly 2MB lampret 7998d 16h /
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 7998d 16h /
957 Flash at 0x04000000 RAM at 0x00000000. Only MMU test works. simons 7999d 03h /
956 Changed to work with or32-uclinux tool chain. Everything works except keyboard test. simons 7999d 07h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.