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Rev Log message Author Age Path
19 Update synthesis result homer.xing 4499d 13h /
18 add synthesis result homer.xing 4499d 13h /
17 use logic for $f3m_mux6$ homer.xing 4499d 15h /
16 Add synthesis configuration files homer.xing 4499d 18h /
15 add document. ha ha ha homer.xing 4499d 19h /
14 Move constraint file homer.xing 4499d 20h /
13 Add document and synthesis directories homer.xing 4499d 20h /
12 Simplify the interface of the core. homer.xing 4499d 20h /
11 Cheers! as fast as a rocket homer.xing 4500d 16h /
10 Ho ho, better circuit homer.xing 4501d 10h /
9 Add constrains file for ISE homer.xing 4502d 14h /
8 Finished Tate Pairing. Ha ha ha homer.xing 4502d 15h /
7 Finish inversion @ f33m homer.xing 4510d 20h /
6 add testbench for $f33m$. homer.xing 4511d 19h /
5 rename director : verilog/ -> rtl/ homer.xing 4511d 19h /
4 add testbench homer.xing 4512d 17h /
3 finish Duursma Lee algorithm. doing f33m module homer.xing 4512d 17h /
2 upload code for Duursma-Lee algorithm. I am still developing them. homer.xing 4513d 17h /
1 The project and the structure was created root 4513d 17h /

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