URL https://opencores.org/ocsvn/pairing/pairing/trunk

Subversion Repositories pairing

[/] - Rev 21

Rev	Log message	Author	Age	Path
21	Add detailed input data capture condition in the document	homer.xing	4497d 04h	/
20	Add a module and a testbench for Xilinx ISE post-route simulation	homer.xing	4498d 06h	/
19	Update synthesis result	homer.xing	4498d 23h	/
18	add synthesis result	homer.xing	4498d 23h	/
17	use logic for $f3m_mux6$	homer.xing	4499d 01h	/
16	Add synthesis configuration files	homer.xing	4499d 04h	/
15	add document. ha ha ha	homer.xing	4499d 05h	/
14	Move constraint file	homer.xing	4499d 06h	/
13	Add document and synthesis directories	homer.xing	4499d 06h	/
12	Simplify the interface of the core.	homer.xing	4499d 06h	/
11	Cheers! as fast as a rocket	homer.xing	4500d 02h	/
10	Ho ho, better circuit	homer.xing	4500d 20h	/
9	Add constrains file for ISE	homer.xing	4502d 00h	/
8	Finished Tate Pairing. Ha ha ha	homer.xing	4502d 00h	/
7	Finish inversion @ f33m	homer.xing	4510d 05h	/
6	add testbench for $f33m$.	homer.xing	4511d 05h	/
5	rename director : verilog/ -> rtl/	homer.xing	4511d 05h	/
4	add testbench	homer.xing	4512d 03h	/
3	finish Duursma Lee algorithm. doing f33m module	homer.xing	4512d 03h	/
2	upload code for Duursma-Lee algorithm. I am still developing them.	homer.xing	4513d 03h	/