URL https://opencores.org/ocsvn/pairing/pairing/trunk

Subversion Repositories pairing

[/] - Rev 24

Rev	Log message	Author	Age	Path
24	LGPL claim in each source hdl file	homer.xing	4508d 09h	/
23	LGPL license text	homer.xing	4508d 09h	/
22	Change TAB to space	homer.xing	4508d 11h	/
21	Add detailed input data capture condition in the document	homer.xing	4508d 11h	/
20	Add a module and a testbench for Xilinx ISE post-route simulation	homer.xing	4509d 13h	/
19	Update synthesis result	homer.xing	4510d 07h	/
18	add synthesis result	homer.xing	4510d 07h	/
17	use logic for $f3m_mux6$	homer.xing	4510d 08h	/
16	Add synthesis configuration files	homer.xing	4510d 11h	/
15	add document. ha ha ha	homer.xing	4510d 13h	/
14	Move constraint file	homer.xing	4510d 13h	/
13	Add document and synthesis directories	homer.xing	4510d 13h	/
12	Simplify the interface of the core.	homer.xing	4510d 14h	/
11	Cheers! as fast as a rocket	homer.xing	4511d 10h	/
10	Ho ho, better circuit	homer.xing	4512d 04h	/
9	Add constrains file for ISE	homer.xing	4513d 07h	/
8	Finished Tate Pairing. Ha ha ha	homer.xing	4513d 08h	/
7	Finish inversion @ f33m	homer.xing	4521d 13h	/
6	add testbench for $f33m$.	homer.xing	4522d 13h	/
5	rename director : verilog/ -> rtl/	homer.xing	4522d 13h	/