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Rev Log message Author Age Path
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7628d 09h /
103 Added test application and modified files to support it. mihad 7675d 06h /
102 Cleanup! mihad 7675d 06h /
101 Added simulation files. mihad 7675d 06h /
100 Cleanup! mihad 7675d 07h /
99 Cleanup! mihad 7675d 07h /
98 Cleanup. mihad 7675d 07h /
97 Doing a little bit of cleanup. mihad 7675d 07h /
96 Update! mihad 7675d 07h /
95 Removed this file, because it was too large - long download time. mihad 7675d 07h /
94 Changed one critical PCI bus signal logic. mihad 7675d 07h /
93 Added a test application! mihad 7675d 14h /
92 Update! mihad 7675d 15h /
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7711d 05h /
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7711d 05h /
89 Burst 2 error fixed. mihad 7747d 05h /
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 7753d 04h /
87 Updated acording to RTL changes. mihad 7765d 02h /
86 Entered the option to disable no response counter in wb master. mihad 7765d 02h /
85 Changed Vendor ID defines. mihad 7765d 06h /

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