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Rev Log message Author Age Path
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7637d 18h /
103 Added test application and modified files to support it. mihad 7684d 16h /
102 Cleanup! mihad 7684d 16h /
101 Added simulation files. mihad 7684d 16h /
100 Cleanup! mihad 7684d 16h /
99 Cleanup! mihad 7684d 16h /
98 Cleanup. mihad 7684d 16h /
97 Doing a little bit of cleanup. mihad 7684d 16h /
96 Update! mihad 7684d 17h /
95 Removed this file, because it was too large - long download time. mihad 7684d 17h /
94 Changed one critical PCI bus signal logic. mihad 7684d 17h /
93 Added a test application! mihad 7685d 00h /
92 Update! mihad 7685d 00h /
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7720d 14h /
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7720d 14h /
89 Burst 2 error fixed. mihad 7756d 15h /
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 7762d 14h /
87 Updated acording to RTL changes. mihad 7774d 11h /
86 Entered the option to disable no response counter in wb master. mihad 7774d 11h /
85 Changed Vendor ID defines. mihad 7774d 16h /

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