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Rev Log message Author Age Path
118 Some minor changes due to changes in core. tadejm 7614d 12h /
117 WB Master is now WISHBONE B3 compatible. tadejm 7614d 12h /
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7614d 12h /
115 Added signals for WB Master B3. tadejm 7614d 13h /
114 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7621d 15h /
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7621d 15h /
112 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7621d 20h /
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7621d 20h /
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.
mihad 7623d 19h /
109 There was missing path to hdl.var file. tadejm 7627d 17h /
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7627d 17h /
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7627d 17h /
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7632d 15h /
105 Wrong pci_bridge32.v file included in the project! mihad 7637d 23h /
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7638d 01h /
103 Added test application and modified files to support it. mihad 7684d 22h /
102 Cleanup! mihad 7684d 22h /
101 Added simulation files. mihad 7684d 22h /
100 Cleanup! mihad 7684d 22h /
99 Cleanup! mihad 7684d 23h /

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