URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

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Rev	Log message	Author	Age	Path
118	Some minor changes due to changes in core.	tadejm	7605d 10h	/
117	WB Master is now WISHBONE B3 compatible.	tadejm	7605d 10h	/
116	Corrected bug when writing to FIFO (now it is registered).	tadejm	7605d 10h	/
115	Added signals for WB Master B3.	tadejm	7605d 10h	/
114	This commit was manufactured by cvs2svn to create tag 'rel_7'.		7612d 13h	/
113	ifdefs moved to thier own lines, this confuses some of the tools.	simons	7612d 13h	/
112	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7612d 18h	/
111	synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.	simons	7612d 18h	/
110	Module that converts slave WISHBONE B3 accesses to WISHBONE B2 accesses with CAB.	mihad	7614d 17h	/
109	There was missing path to hdl.var file.	tadejm	7618d 14h	/
108	Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.	tadejm	7618d 14h	/
107	Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry.	tadejm	7618d 15h	/
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7623d 13h	/
105	Wrong pci_bridge32.v file included in the project!	mihad	7628d 20h	/
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7628d 23h	/
103	Added test application and modified files to support it.	mihad	7675d 20h	/
102	Cleanup!	mihad	7675d 20h	/
101	Added simulation files.	mihad	7675d 20h	/
100	Cleanup!	mihad	7675d 20h	/
99	Cleanup!	mihad	7675d 20h	/

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[/] - Rev 118

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