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Rev Log message Author Age Path
128 Some warning cleanup. simons 7494d 17h /
127 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7502d 10h /
126 ifdef - endif statements put in separate lines for flint compatibility. simons 7502d 10h /
125 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7540d 17h /
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7540d 17h /
123 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7547d 17h /
122 mbist signals updated according to newest convention markom 7547d 17h /
121 This commit was manufactured by cvs2svn to create tag 'rel_WB_B3'. 7604d 05h /
120 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7604d 05h /
119 Added support for WB B3. Some testcases were updated. tadejm 7604d 05h /
118 Some minor changes due to changes in core. tadejm 7604d 05h /
117 WB Master is now WISHBONE B3 compatible. tadejm 7604d 05h /
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7604d 05h /
115 Added signals for WB Master B3. tadejm 7604d 06h /
114 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7611d 08h /
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7611d 08h /
112 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7611d 13h /
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7611d 13h /
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.
mihad 7613d 12h /
109 There was missing path to hdl.var file. tadejm 7617d 10h /

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