URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] - Rev 54

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7965d 18h	/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7965d 22h	/
52	Oops, never before noticed that OC header is missing	mihad	7966d 02h	/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7966d 02h	/
50	Got rid of undef directives	mihad	7968d 18h	/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7968d 18h	/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7968d 19h	/
47	Known issues repaired	mihad	7969d 00h	/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	7973d 19h	/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7975d 00h	/
44	Added for testing of Configuration Cycles Type 1	mihad	7975d 01h	/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	7975d 01h	/
42	Removed out of date files	mihad	7987d 01h	/
41	This commit was manufactured by cvs2svn to create tag 'rel_00'.		8065d 16h	/
40	From these Wrod files PDF were created - added future improvements	tadej	8065d 16h	/
39	File not needed	tadej	8065d 17h	/
38	This file is not needed	tadej	8065d 20h	/
37	These files are not needed any more	tadej	8065d 20h	/
36	* empty log message *	tadej	8065d 20h	/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8120d 04h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pci

[/] - Rev 54

Filtering Options