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Rev Log message Author Age Path
58 Removed all logic from asynchronous reset network mihad 7935d 06h /
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7935d 12h /
56 Number of state bits define was removed mihad 7936d 03h /
55 Changed state machine encoding to true one-hot mihad 7936d 04h /
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7969d 05h /
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7969d 09h /
52 Oops, never before noticed that OC header is missing mihad 7969d 13h /
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7969d 13h /
50 Got rid of undef directives mihad 7972d 05h /
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7972d 05h /
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7972d 05h /
47 Known issues repaired mihad 7972d 11h /
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7977d 05h /
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7978d 11h /
44 Added for testing of Configuration Cycles Type 1 mihad 7978d 12h /
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7978d 12h /
42 Removed out of date files mihad 7990d 12h /
41 This commit was manufactured by cvs2svn to create tag 'rel_00'. 8069d 03h /
40 From these Wrod files PDF were created - added future improvements tadej 8069d 03h /
39 File not needed tadej 8069d 03h /

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