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Rev	Log message	Author	Age	Path
66	Changed empty status generation in pciw_fifo_control.v	mihad	7932d 21h	/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7935d 20h	/
64	The testcase I just added in previous revision repaired	mihad	7935d 22h	/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7936d 00h	/
62	Added BIST signals for RAMs.	mihad	7938d 17h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7946d 17h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7946d 17h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7946d 18h	/
58	Removed all logic from asynchronous reset network	mihad	7951d 18h	/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7952d 00h	/
56	Number of state bits define was removed	mihad	7952d 15h	/
55	Changed state machine encoding to true one-hot	mihad	7952d 15h	/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7985d 17h	/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7985d 20h	/
52	Oops, never before noticed that OC header is missing	mihad	7986d 01h	/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7986d 01h	/
50	Got rid of undef directives	mihad	7988d 17h	/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7988d 17h	/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7988d 17h	/
47	Known issues repaired	mihad	7988d 23h	/

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