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Rev	Log message	Author	Age	Path
72	* empty log message *	mihad	7864d 15h	/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7872d 07h	/
70	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7909d 15h	/
69	Changed BIST signal names etc..	mihad	7909d 15h	/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7913d 00h	/
67	Changed BIST signals for RAMs.	tadejm	7913d 05h	/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7916d 15h	/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7919d 14h	/
64	The testcase I just added in previous revision repaired	mihad	7919d 16h	/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7919d 18h	/
62	Added BIST signals for RAMs.	mihad	7922d 11h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7930d 10h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7930d 10h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7930d 12h	/
58	Removed all logic from asynchronous reset network	mihad	7935d 12h	/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7935d 18h	/
56	Number of state bits define was removed	mihad	7936d 09h	/
55	Changed state machine encoding to true one-hot	mihad	7936d 09h	/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7969d 11h	/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7969d 14h	/

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[/] - Rev 72

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