URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] - Rev 77

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7811d 07h	/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7814d 07h	/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7817d 08h	/
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7817d 08h	/
73	Bug fixes, testcases added.	mihad	7817d 08h	/
72	* empty log message *	mihad	7864d 12h	/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7872d 03h	/
70	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7909d 11h	/
69	Changed BIST signal names etc..	mihad	7909d 11h	/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7912d 20h	/
67	Changed BIST signals for RAMs.	tadejm	7913d 01h	/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7916d 12h	/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7919d 10h	/
64	The testcase I just added in previous revision repaired	mihad	7919d 12h	/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7919d 14h	/
62	Added BIST signals for RAMs.	mihad	7922d 07h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7930d 07h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7930d 07h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7930d 08h	/
58	Removed all logic from asynchronous reset network	mihad	7935d 08h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pci

[/] - Rev 77

Filtering Options