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Rev Log message Author Age Path
83 Cleaned up the code. No functional changes. mihad 7801d 08h /
82 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7815d 04h /
81 Updated synchronization in top level fifo modules. mihad 7815d 04h /
80 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7818d 09h /
79 Updated. mihad 7818d 09h /
78 Old files with wrong names removed. mihad 7818d 09h /
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7818d 09h /
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7821d 09h /
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7824d 10h /
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7824d 10h /
73 Bug fixes, testcases added. mihad 7824d 10h /
72 *** empty log message *** mihad 7871d 14h /
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7879d 06h /
70 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7916d 13h /
69 Changed BIST signal names etc.. mihad 7916d 13h /
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7919d 23h /
67 Changed BIST signals for RAMs. tadejm 7920d 03h /
66 Changed empty status generation in pciw_fifo_control.v mihad 7923d 14h /
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7926d 12h /
64 The testcase I just added in previous revision repaired mihad 7926d 14h /

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