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Rev Log message Author Age Path
43 Trying to organize pci master tests by function, label them, to avoid duplication.
Adding pci_target_test file, to start the work on the target side.		 bbeaver 8431d 07h /
42 trying to make master test framework easier to use bbeaver 8431d 19h /
41 odds and ends in the master. Parity mostly. Not debugged. bbeaver 8432d 02h /
40 more improvements to master bbeaver 8432d 15h /
39 Master Retries seem OK.
Working on flushing, increasing test coverage.		 bbeaver 8432d 20h /
38 working on master. bbeaver 8433d 18h /
37 Getting Master Abort Timers to have correct values bbeaver 8437d 20h /
36 more progress onthe master side bbeaver 8438d 06h /
35 Made the compromise that the FIFOs and the PCI Bus
will be the same width. No 32/64 combinations.
Working on Master.		 bbeaver 8439d 00h /
34 Starting to remove extra logic in PCI Master bbeaver 8445d 21h /
33 Polishing the PCI Master. bbeaver 8446d 19h /
32 Starting to get simplified Master State Machine to do something.
NOTE: This has not been optimized to fit into CLB's yet.		 bbeaver 8451d 21h /
31 Still messing with Master State Machine bbeaver 8460d 21h /
30 Fixed various problems with new function for Master State Machine. bbeaver 8467d 22h /
29 Changed Master State Machine to be function based.
This will make it possible to pipeline it better.		 bbeaver 8468d 00h /
28 Renamed all the combinational control signals to have
names ending in "_critical".		 bbeaver 8468d 03h /
27 Massive edit to start changing many `defines into Parameters.
This MIGHT (?) make it possible to have more than 1 PCI interface,
but with different bus sizes.
On the other hand, it might be an idiotic change in style.		 bbeaver 8468d 20h /
26 Finished code formatting changes.
Need to add state bit which knows to Retry or not.
Now trying to get Master State Machine to actually operate.		 bbeaver 8469d 01h /
25 Continuing to improve the Master. bbeaver 8469d 22h /
24 Finally got Master to start capturing Retry Address and Data correctly. bbeaver 8470d 04h /

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