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Rev	Log message	Author	Age	Path
36	Ensure correct read of CSR after stall	skordal	3300d 13h	/
35	Prevent jumping/branching when stalling	skordal	3300d 13h	/
34	Prevent flushing the pipeline if it is stalling	skordal	3300d 13h	/
33	Ensure correct read of CSR after stall	skordal	3300d 13h	/
32	Prevent jumping/branching when stalling	skordal	3303d 10h	/
31	Prevent flushing the pipeline if it is stalling	skordal	3303d 11h	/
30	Add testcase for a combination of instructions that fail when using cache	skordal	3305d 15h	/
29	Add reset functionality for the WB arbiter state machine	skordal	3308d 11h	/
28	Add rudimentary User's manual	skordal	3314d 10h	/
27	Prevent exceptions from being taken while stalling	skordal	3314d 12h	/
26	Prevent exceptions from being taken while stalling Jumping to an exception handler while stalling and waiting for a load/store instruction to finish can cause undefined results from the load/store instruction. This actually fixes the issue mentioned in revision r20.	skordal	3314d 15h	/
25	Add placeholder cache modules and a wishbone arbiter	skordal	3316d 19h	/
24	Remove unused STRINGIFY macros	skordal	3317d 08h	/
23	Create branch to use for implementing a cache	skordal	3317d 08h	/
22	Fix the potato_get_badvaddr() macro	skordal	3317d 09h	/
21	Upgrade the example design to use a 60 MHz system clock	skordal	3317d 09h	/
20	Fix SHA256 benchmark crash by storing all registers on exception handler entry This problem will disappear when the processor is updated to conform to the new supervisor specification, which will allow us to use a compiler that conforms to the new "official" ABI.	skordal	3317d 09h	/
19	SHA256 benchmark: allow compiler to inline at will	skordal	3317d 09h	/
18	instr_misalign_check: add do_jump to sensitivity list	skordal	3319d 09h	/
17	Improve detection of unaligned instructions	skordal	3323d 16h	/

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[/] - Rev 36

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