OpenCores
URL https://opencores.org/ocsvn/r2000/r2000/trunk

Subversion Repositories r2000

[/] - Rev 17

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
17 - UnFonctional Modifications: Change the name of the address port of "CP0". ameziti 5973d 09h /
16 - Remove All generable files from the project. ameziti 5973d 17h /
15 - UnFonctional Modifications.
- Change the "CP0" define to "EXCEPTION".		 ameziti 5973d 18h /
14 Remove unnecessary files from project. ameziti 5974d 02h /
13 - To simplify the exception traitement: Instruction are executed serialy.
- Exception event must be treated CONCURRENTLY with the other event that stall the pipeline.		 ameziti 5974d 02h /
12 To simplify the exception traitement: Instruction are executed serialy. ameziti 5974d 03h /
11 Exception event must be treated CONCURRENTLY with the other event that stall the pipeline. ameziti 5974d 03h /
10 Modification of the CP0. ameziti 5974d 03h /
9 When D-Cache miss, there's no need to stall MEMWB and freeze WB.
The solution is to flush MEMWB only.		 ameziti 5974d 03h /
8 Enhancement of the "Controler specification doc". ameziti 5977d 03h /
7 Add Pipeline Controler specification documentation. ameziti 5978d 02h /
6 When D-Cache miss, there's no need to stall MEMWB and freeze WB.
The solution is to flush MEMWB only.		 ameziti 5978d 04h /
5 Remove the Multiple Arithmetic Unit fonction.
- The Pipeline must stall when Mult/Div unit is busy.
- Whether there's a mflo or mfhi.
- see `define MULTIPLE_ALU		 ameziti 5979d 01h /
4 Add Soc Image in the Specification documentation ameziti 6000d 04h /
3 This commit was manufactured by cvs2svn to create tag 'arelease'. 6001d 12h /
2 First Import the project on the opencores.org CVS server ameziti 6001d 12h /
1 Standard project directories initialized by cvs2svn. 6001d 12h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.