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Rev Log message Author Age Path
152 Test bench oriented modifications jguarin2002 4478d 14h /
151 Previous Work to generate test benching jguarin2002 4537d 10h /
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4551d 07h /
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4551d 10h /
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4551d 10h /
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4553d 22h /
146 Interruption Machine jguarin2002 4561d 16h /
145 State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig jguarin2002 4566d 06h /
144 The commented part of DPC was erased, and no longer needed. jguarin2002 4573d 10h /
143 working on result queue sync decoding signals jguarin2002 4578d 02h /
142 Additions for the State Machine jguarin2002 4583d 00h /
141 Syncing: its awful work: input adresses decoded to include the instructions queue also.... jguarin2002 4650d 02h /
140 Syncing: its awful work..... jguarin2002 4650d 07h /
139 Sync jguarin2002 4661d 22h /
138 enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes jguarin2002 4666d 13h /
137 Syncing with enables and eleminated all the register outputs since none block should carry on a register output jguarin2002 4672d 14h /
136 gogogo jguarin2002 4675d 01h /
135 Correction on conectiveness of Datapath Control... jguarin2002 4679d 01h /
134 State Machine, for addressing counting, internal writing & reading control and interruption generation jguarin2002 4680d 21h /
133 Added the instructions queue jguarin2002 4682d 13h /

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