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Rev Log message Author Age Path
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4554d 21h /
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4555d 09h /
156 Test Bench Beta 0.1 jguarin2002 4555d 21h /
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4558d 21h /
154 rt_tb.vhd: This file will be used as the test bench main file jguarin2002 4561d 13h /
153 last modifications for tb_compiler.py compliance jguarin2002 4561d 13h /
152 Test bench oriented modifications jguarin2002 4565d 14h /
151 Previous Work to generate test benching jguarin2002 4624d 10h /
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4638d 07h /
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4638d 11h /
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4638d 11h /
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4640d 23h /
146 Interruption Machine jguarin2002 4648d 17h /
145 State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig jguarin2002 4653d 07h /
144 The commented part of DPC was erased, and no longer needed. jguarin2002 4660d 10h /
143 working on result queue sync decoding signals jguarin2002 4665d 03h /
142 Additions for the State Machine jguarin2002 4670d 01h /
141 Syncing: its awful work: input adresses decoded to include the instructions queue also.... jguarin2002 4737d 02h /
140 Syncing: its awful work..... jguarin2002 4737d 08h /
139 Sync jguarin2002 4748d 22h /

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