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Rev	Log message	Author	Age	Path
163	dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions.	jguarin2002	4453d 11h	/
162	Señales para evaluar en simulación funcional	jguarin2002	4453d 11h	/
161	Changes for the sake of the firsts simulation tracking results	jguarin2002	4455d 02h	/
160	Corrections derived from simulation debugging	jguarin2002	4459d 18h	/
159	wrcycle\!\? No\! rwcycle....	jguarin2002	4461d 04h	/
158	Changing std_logic_vector types to my custom far more convinients xfloat32\!	jguarin2002	4461d 08h	/
157	For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim	jguarin2002	4461d 20h	/
156	Test Bench Beta 0.1	jguarin2002	4462d 08h	/
155	Changes applied prior to testbenching using the script tb_compiler.py	jguarin2002	4465d 09h	/
154	rt_tb.vhd: This file will be used as the test bench main file	jguarin2002	4468d 00h	/
153	last modifications for tb_compiler.py compliance	jguarin2002	4468d 00h	/
152	Test bench oriented modifications	jguarin2002	4472d 02h	/
151	Previous Work to generate test benching	jguarin2002	4530d 22h	/
150	First Beta of RayTrac for a total size of 3874 lcells. Great Result\!	jguarin2002	4544d 19h	/
149	Results Queue writing signals set on a single standard logic vector rather than in individual bits	jguarin2002	4544d 22h	/
148	Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B	jguarin2002	4544d 22h	/
147	Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified.	jguarin2002	4547d 10h	/
146	Interruption Machine	jguarin2002	4555d 04h	/
145	State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig	jguarin2002	4559d 18h	/
144	The commented part of DPC was erased, and no longer needed.	jguarin2002	4566d 22h	/

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Subversion Repositories raytrac

[/] - Rev 163

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