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Rev	Log message	Author	Age	Path
170	Slim, suited to fit, elegant and small, optimized and well designed single precision floating point I3E754 32 bit adder	jguarin2002	4461d 06h	/
169	Long Stupid, version of a 32 bit floating point I3E754 Adder	jguarin2002	4461d 06h	/
168	Added a display function for vectorblock02	jguarin2002	4463d 20h	/
167	Corrections on the moment the dot product and normalization queues are "rd_ack\'ed", they were a cycle earlier than they should causing pipeline desync	jguarin2002	4463d 20h	/
166	A strong revision on the decodification of the places to shift must be done..... I mean s5factor is EATING memory (Altera Synthesis), perhaps thats a better way	jguarin2002	4464d 06h	/
165	Fix on the decodification of factor to add or sub to the final exponent after mantissa normalization (Stage 5, s5factor)	jguarin2002	4464d 15h	/
164	reverting the not(s0delta(7)) change on revision 163 to s0delta(7) again	jguarin2002	4465d 17h	/
163	dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions.	jguarin2002	4465d 19h	/
162	Señales para evaluar en simulación funcional	jguarin2002	4465d 19h	/
161	Changes for the sake of the firsts simulation tracking results	jguarin2002	4467d 10h	/
160	Corrections derived from simulation debugging	jguarin2002	4472d 02h	/
159	wrcycle\!\? No\! rwcycle....	jguarin2002	4473d 12h	/
158	Changing std_logic_vector types to my custom far more convinients xfloat32\!	jguarin2002	4473d 16h	/
157	For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim	jguarin2002	4474d 04h	/
156	Test Bench Beta 0.1	jguarin2002	4474d 16h	/
155	Changes applied prior to testbenching using the script tb_compiler.py	jguarin2002	4477d 16h	/
154	rt_tb.vhd: This file will be used as the test bench main file	jguarin2002	4480d 08h	/
153	last modifications for tb_compiler.py compliance	jguarin2002	4480d 08h	/
152	Test bench oriented modifications	jguarin2002	4484d 10h	/
151	Previous Work to generate test benching	jguarin2002	4543d 06h	/

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[/] - Rev 170

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