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Rev Log message Author Age Path
209 Working towards a DMA oriented RayTRac jguarin2002 4360d 08h /
208 Working towards a DMA oriented RayTRac jguarin2002 4360d 08h /
207 Working towards a DMA oriented RayTRac jguarin2002 4360d 08h /
206 Working towards a DMA oriented RayTRac jguarin2002 4360d 08h /
205 Working towards a DMA oriented RayTRac jguarin2002 4360d 08h /
204 Working towards a DMA oriented RayTRac jguarin2002 4360d 08h /
203 Working towards a DMA oriented RayTRac jguarin2002 4360d 08h /
202 Working towards a DMA oriented RayTRac jguarin2002 4360d 08h /
201 files no longer needed im.vhd and fadd32long.vhd jguarin2002 4360d 08h /
200 raytrac_control.vhd: rtl that describes, the raytrac control registers, the avalaon memory mapped slave interface, the avalon memory mapped master interface, the controlling state machine, the input and output buffers jguarin2002 4360d 08h /
199 Check out in the design document for changes made on Load logic, a load chain has been added to Memblock I/O and several memory blocks were removed, under construction, this version WONT in any means work jguarin2002 4376d 14h /
198 Check out for the best out for the best organization so the datapath does not consume to many logic cells jguarin2002 4376d 14h /
197 Chnages on interconnectivity: Check out the SGDMA Sheets jguarin2002 4386d 15h /
196 raytrac+sg_dma+raytrac. Step One, the DPC is transformed. Now there are five instructions (check the design document), theres no full queue sync event, there are only four result queues and only 3 add fp 32 b adders rather than 4. Even it seems like a reduction has taken place, decodification efforts take place when decoding multiplexation from arithmetic blocks towards the resulting queues jguarin2002 4390d 02h /
195 Document advance and changes in the design jguarin2002 4392d 23h /
194 Work In Progress jguarin2002 4408d 05h /
193 WIP: Main Document jguarin2002 4409d 02h /
192 Some change I dont realize what is it in the design document (xls) jguarin2002 4409d 14h /
191 Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. jguarin2002 4409d 14h /
190 M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... jguarin2002 4413d 22h /

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