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Rev Log message Author Age Path
245 Avances pequenos en los documentos jguarin2002 4303d 06h /
244 Changed the directory structure a little bit, there is now wide arith (which encapsulates in a single RTL 3 adders or 3 adders jguarin2002 4306d 05h /
243 The Registers BASE+1, BASE+2, BASE+3 are used now for debugging purposes jguarin2002 4306d 05h /
242 AS1 produced an unnoticed delay, the compiler geenerated an extra stage..... so a delay constant was added to sync this extra stage with the operation via ssync_chain jguarin2002 4306d 05h /
241 fmul32 x 6 multipliers wide jguarin2002 4307d 01h /
240 last minute correction jguarin2002 4307d 05h /
239 wide multiplicator added to avoid optimization jguarin2002 4307d 05h /
238 wide multiplicator added to avoid optimization jguarin2002 4307d 05h /
237 corrected errors in raytrac.vhd jguarin2002 4307d 07h /
236 Tunnning delay added to q0 queue jguarin2002 4307d 10h /
235 Tunnning delay added to q0 queue jguarin2002 4307d 10h /
234 raytrac update nothing major jguarin2002 4308d 10h /
233 raytrac sopc component updated jguarin2002 4308d 10h /
232 raytrac sopc component updated jguarin2002 4308d 10h /
231 nfetch address counter implemented in a whole register for convinience jguarin2002 4308d 11h /
230 RC 1.0 Previous rev(228), is functional and even more than this one, but is bigger and is for debugging jguarin2002 4313d 13h /
229 Total RtEngine Hardware, BUT, problems with interconnection... perhaps theres a problem with long path on ssumando5 jguarin2002 4314d 13h /
228 Fixed a BUG where big differences betweeen exponents difference suffered from miss-signedness because of the width of the result was 1 bit narrower, and still its highest significant bit was taken as the sign, in result big differences in where taken as negative results... leading to situations like A+0=0 cause the exponent chosen as the big one was the zero's (-127) leading to an unexpected 0 in the result. The bug was fixed by correcting the signedness of the operation and making the result less narrower in one bit. jguarin2002 4316d 06h /
227 Fixed a BUG where big differences betweeen exponents difference suffered from miss-signedness because of the width of the result was 1 bit narrower, and still its highest significant bit was taken as the sign, in result big differences in where taken as negative results... leading to situations like A+0=0 cause the exponent chosen as the big one was the zero's (-127) leading to an unexpected 0 in the result. The bug was fixed by correcting the signedness of the operation and making the result less narrower in one bit. jguarin2002 4316d 10h /
226 Documento 90%, falta el glosario de siglas, el anexo de referencia de RTLs, el capitulo 9 (trazador de rayos) y la bibiliografia jguarin2002 4316d 11h /

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