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Rev Log message Author Age Path
251 Es claro.... jguarin2002 4267d 01h /
250 Design changed..... doubts about OS using jguarin2002 4267d 01h /
249 Using a register as a 66.5 MHZ timer counter jguarin2002 4269d 16h /
248 Corrected an error on the normal jguarin2002 4277d 21h /
247 Advance in application... but some normalization problems had popped up jguarin2002 4278d 13h /
246 framework for conditional and accumulative operations DESCRIBED NOT IMPLEMENTED jguarin2002 4285d 01h /
245 Avances pequenos en los documentos jguarin2002 4297d 20h /
244 Changed the directory structure a little bit, there is now wide arith (which encapsulates in a single RTL 3 adders or 3 adders jguarin2002 4300d 18h /
243 The Registers BASE+1, BASE+2, BASE+3 are used now for debugging purposes jguarin2002 4300d 19h /
242 AS1 produced an unnoticed delay, the compiler geenerated an extra stage..... so a delay constant was added to sync this extra stage with the operation via ssync_chain jguarin2002 4300d 19h /
241 fmul32 x 6 multipliers wide jguarin2002 4301d 15h /
240 last minute correction jguarin2002 4301d 19h /
239 wide multiplicator added to avoid optimization jguarin2002 4301d 19h /
238 wide multiplicator added to avoid optimization jguarin2002 4301d 19h /
237 corrected errors in raytrac.vhd jguarin2002 4301d 21h /
236 Tunnning delay added to q0 queue jguarin2002 4302d 00h /
235 Tunnning delay added to q0 queue jguarin2002 4302d 00h /
234 raytrac update nothing major jguarin2002 4303d 00h /
233 raytrac sopc component updated jguarin2002 4303d 00h /
232 raytrac sopc component updated jguarin2002 4303d 00h /

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