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Rev Log message Author Age Path
253 .... jguarin2002 4270d 11h /
252 Performance Results on the Raytrac jguarin2002 4271d 15h /
251 Es claro.... jguarin2002 4271d 15h /
250 Design changed..... doubts about OS using jguarin2002 4271d 15h /
249 Using a register as a 66.5 MHZ timer counter jguarin2002 4274d 06h /
248 Corrected an error on the normal jguarin2002 4282d 11h /
247 Advance in application... but some normalization problems had popped up jguarin2002 4283d 03h /
246 framework for conditional and accumulative operations DESCRIBED NOT IMPLEMENTED jguarin2002 4289d 15h /
245 Avances pequenos en los documentos jguarin2002 4302d 10h /
244 Changed the directory structure a little bit, there is now wide arith (which encapsulates in a single RTL 3 adders or 3 adders jguarin2002 4305d 09h /
243 The Registers BASE+1, BASE+2, BASE+3 are used now for debugging purposes jguarin2002 4305d 09h /
242 AS1 produced an unnoticed delay, the compiler geenerated an extra stage..... so a delay constant was added to sync this extra stage with the operation via ssync_chain jguarin2002 4305d 09h /
241 fmul32 x 6 multipliers wide jguarin2002 4306d 05h /
240 last minute correction jguarin2002 4306d 09h /
239 wide multiplicator added to avoid optimization jguarin2002 4306d 09h /
238 wide multiplicator added to avoid optimization jguarin2002 4306d 09h /
237 corrected errors in raytrac.vhd jguarin2002 4306d 11h /
236 Tunnning delay added to q0 queue jguarin2002 4306d 14h /
235 Tunnning delay added to q0 queue jguarin2002 4306d 14h /
234 raytrac update nothing major jguarin2002 4307d 14h /

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