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Rev Log message Author Age Path
45 Magic is already written... now we shall set the testbench on fire\! jguarin2002 4942d 03h /
44 All components in the test bench are now instantiated what is left now is the magic, menaing the test algorithm... also rom memories with crash test dummies are addedsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mifsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mif... jguarin2002 4943d 04h /
43 Nothing to say, just working on the Test Bench... jguarin2002 4943d 12h /
42 no comment no tb yet: jguarin2002 4944d 05h /
41 Ram for the massses\!\!\! jguarin2002 4946d 16h /
40 test bench changes..... jguarin2002 4946d 16h /
39 Perhaps its a good idea to have a todo.txt file under version control jguarin2002 4948d 13h /
38 Tb ggodies jguarin2002 4950d 04h /
37 Testbenchgoodies jguarin2002 4950d 04h /
36 testbench for rtengine test jguarin2002 4950d 15h /
35 oops stderr -> stdout, fixed jguarin2002 4950d 15h /
34 No need for .h jguarin2002 4950d 17h /
33 Program to create a MIF (memory initialization file) in order to simulate RtEngine jguarin2002 4954d 03h /
32 carry_logic parameter added to uf entity jguarin2002 4956d 18h /
31 enable signal retaken, and error corrected, a really big mistake jguarin2002 4957d 03h /
30 enable signal retaken... ooops a little lapsus jguarin2002 4957d 03h /
29 enable signal dropped... jguarin2002 4957d 03h /
28 fix fow q10 on stage0 to stage1 opcode signal... i was not sure if the thing was the right thing. jguarin2002 4957d 03h /
27 Optimized code, using IEEE libraries and extra parameters to make a more legible code jguarin2002 4971d 01h /
26 Corrections on opcoder jguarin2002 4971d 05h /

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