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Rev Log message Author Age Path
47 Started making tests, but dont understand quite well the mechanics of Modelsim. Change Arithpack for quicker multiplier and memory instantiation jguarin2002 4968d 01h /
46 simplified memory path jguarin2002 4968d 03h /
45 Magic is already written... now we shall set the testbench on fire\! jguarin2002 4969d 15h /
44 All components in the test bench are now instantiated what is left now is the magic, menaing the test algorithm... also rom memories with crash test dummies are addedsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mifsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mif... jguarin2002 4970d 16h /
43 Nothing to say, just working on the Test Bench... jguarin2002 4971d 00h /
42 no comment no tb yet: jguarin2002 4971d 17h /
41 Ram for the massses\!\!\! jguarin2002 4974d 04h /
40 test bench changes..... jguarin2002 4974d 05h /
39 Perhaps its a good idea to have a todo.txt file under version control jguarin2002 4976d 02h /
38 Tb ggodies jguarin2002 4977d 16h /
37 Testbenchgoodies jguarin2002 4977d 17h /
36 testbench for rtengine test jguarin2002 4978d 03h /
35 oops stderr -> stdout, fixed jguarin2002 4978d 03h /
34 No need for .h jguarin2002 4978d 05h /
33 Program to create a MIF (memory initialization file) in order to simulate RtEngine jguarin2002 4981d 16h /
32 carry_logic parameter added to uf entity jguarin2002 4984d 07h /
31 enable signal retaken, and error corrected, a really big mistake jguarin2002 4984d 15h /
30 enable signal retaken... ooops a little lapsus jguarin2002 4984d 15h /
29 enable signal dropped... jguarin2002 4984d 15h /
28 fix fow q10 on stage0 to stage1 opcode signal... i was not sure if the thing was the right thing. jguarin2002 4984d 15h /

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