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Rev Log message Author Age Path
15 All testcases are ok. Still needs some tweeks though. magro732 3975d 20h /
14 Most issues solved, testbench issues remains. magro732 3978d 20h /
13 Timeouts are working. magro732 3981d 20h /
12 Backup of recent work, debugging new RioSerial. magro732 3992d 19h /
11 Receiver ready, transmitter is compiling. magro732 3992d 20h /
10 Branch to develop support for parallel symbols. magro732 3992d 20h /
9 Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes) azdem 4034d 08h /
8 Adding signal descriptions in comments. magro732 4077d 21h /
7 Adding missing generic parameters to RioPacketBuffer. magro732 4165d 01h /
6 Adding RioWbBridge. Sorry, no testbench for this one. magro732 4165d 03h /
5 Uploading primitive documentation. magro732 4171d 19h /
4 Adding protocol engine implementing the hardware independent parts of the LP-serial physical specification. magro732 4194d 08h /
3 Adding RioPacketBuffer and testbench. magro732 4195d 00h /
2 Adding RioSwitch and testbench. magro732 4195d 02h /
1 The project and the structure was created root 4196d 08h /

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