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Rev Log message Author Age Path
107 - Added new example for memory testing. cwalter 6374d 10h /
106 - ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT. cwalter 6374d 10h /
105 - OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT. cwalter 6374d 10h /
104 - Added missing signal dmem_data_in. cwalter 6374d 11h /
103 - Added simulation for memory to behavioral.
- Added empty mif file for memory.		 cwalter 6374d 11h /
102 changed data pitch ustadler 6376d 16h /
101 - Signals for memory block where not always set. This resulted in a latch. cwalter 6376d 16h /
100 - Signal clear_in was missing in sensitivity list. cwalter 6376d 16h /
99 - Fixed problem with barrel shifter input signals where a latch has been
synthesized.		 cwalter 6376d 16h /
98 - Applied indenting tool. cwalter 6376d 16h /
97 Fixed bug: only set branch and clear signals if branch is actually executed. jlechner 6376d 17h /
96 - SR register is now computed in ALU stage. cwalter 6376d 17h /
95 - Write back now only updates SR in case of a LOAD. cwalter 6376d 17h /
94 Added signal from ex stage to register lock unit for clearing all register locks
when a branch is executed.		 jlechner 6376d 18h /
93 Changed behavior on branch. Current PC is immeadiately taken from ex stage alu result. jlechner 6376d 18h /
92 Added logic for inserting a nop instruction when the pipeline is cleared. jlechner 6376d 18h /
91 - Computed new SR values from ALU result. cwalter 6376d 18h /
90 Added output signal for clearing all register locks when a branch instruction is executed.
This is necessary because the id stage could have locked registers for an instruction
that is cleared out of the pipeline due to the branch.		 jlechner 6376d 18h /
89 Added input signal for clearing all register locks. jlechner 6376d 18h /
88 - Added new patch for assembler. cwalter 6376d 19h /

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