URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 12

Rev	Log message	Author	Age	Path
12	- Added constant definitions for SR, PC and LR register.	cwalter	6388d 10h	/
11	- Added checks to test if a register has been locked. If it is locked and used in the decoded instruction the stall_out signal is asserted. - Added missing signals to process sensitivity list. - Fixed bug in rY decoding where the value of rZ was used. - Implemented opcode_modifies_rx.	cwalter	6388d 10h	/
10	- added testbench for load immediate and load immediate with high byte.	cwalter	6390d 13h	/
9	- added support for immediate value decoding. - opcode extender now works correctly for load immediate. needed special handling for the high byte bit. - conditional decoder needed special handling for high byte bit.	cwalter	6390d 14h	/
8	Implementation of execute stage and register lock unit. Some changes im RISE package.	jlechner	6390d 17h	/
7	- initial version of instruction decode stage testbench.	cwalter	6409d 10h	/
6	- applied VHDL source code indenter.	cwalter	6409d 10h	/
5	- correct register address width is 4 bit and not 5 bit. - added constants for OPCODES, COND and SR.	cwalter	6409d 10h	/
4	- added decode for rX, rY, rZ. - added decode for opcodes.	cwalter	6409d 10h	/
3	Add pipeline design documents	jlechner	6415d 13h	/
2	Initial commit of project	jlechner	6415d 13h	/
1	Standard project directories initialized by cvs2svn.		6415d 13h	/