URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 129

Rev	Log message	Author	Age	Path
129	Sample assembler program for accessing uart	jlechner	6390d 11h	/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6390d 11h	/
127	Changed high active resets to low active ones.	jlechner	6390d 12h	/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6390d 18h	/
125	Fixed vhdl bugs	trinklhar	6390d 18h	/
124	Assigned UART signals to ports on top-level entity	trinklhar	6390d 18h	/
123	Removed UART again	trinklhar	6390d 19h	/
122	Removed UART again again	trinklhar	6390d 19h	/
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6390d 19h	/
120	Added UART module to memory entity	trinklhar	6390d 19h	/
119	Uart wieder ausgebaut	trinklhar	6391d 14h	/
118	insert Uart address constant	trinklhar	6391d 14h	/
117	Uart im mem_stage	trinklhar	6391d 14h	/
116	writes to uart when write to reg 0	trinklhar	6392d 20h	/
115	* empty log message *	trinklhar	6393d 10h	/
114	Uart 0.3	trinklhar	6394d 15h	/
113	Uart reset funkt	trinklhar	6394d 16h	/
112	Uart drin aber signale nicht eingebunden	trinklhar	6394d 17h	/
111	- Fixed bug where certain opcodes did not check for availability of registers.	cwalter	6397d 09h	/
110	- Added missing file to CVS.	cwalter	6397d 16h	/